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CXA1616N/S
Sync Discriminator for CRT Displays
Description The CXA1616N/S automatically selects one of three types of sync signals - separate sync, composite sync, or sync-on video - to shape the waveform. It is ideally suited as a synchronous signal processor for auto tracking type displays. Features * Output of synchronous signal polarity information is obtainable * Supported polarities and amplitudes of input signals are as follows: -- V. separate sync (positive/negative polarity, 1 to 5Vp-p For capacitor input 1.5 to 5Vp-p) -- H. separate sync (positive/negative polarity, 1 to 5Vp-p) -- Composite sync (positive/negative polarity, 1 to 5Vp-p) -- Sync-on video (negative polarity sync level: 0.2 to 0.6Vp-p, picture level: 0 to 2.1Vp-p) Applications CRT display monitors Pin Configuration (Top View) (SSOP)
VS IN 1
CXA1616N 24 pin SSOP (Plastic)
CXA1616S 22 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage Vcc 14 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 900 mW Operating Condition Supply voltage
Vcc
12 0.5
V
(SDIP)
22 VCC 21 VD 20 V IN 19 V OUT 18 HD
VS IN
1
24 VCC 23 VD 22 V IN 21 V OUT 20 HD 19 PV 18 PH
PVC 2 EVC CS IN PHC EHC VIDEO IN HD SEL TIMING 3 4 5 6 7 8 9
PVC 2 EVC CS IN PHC EHC VIDEO IN HD SEL TIMING 3 4 5 6 7 8 9
17 PV 16 PH 15 EV 14 EH 13 IN/EXT 12 V REF
17 EV 16 EH 15 IN/EXT 14 V REF 13 NC
CLAMP 10 GND 11 NC 12
CLAMP 10 GND 11
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E92Y01C7Y-PS
CXA1616N/S
Block Diagram (SSOP)
PVC EVC
3 V. Ramp Generator Exist Check EV 20 Logic CS IN 4 Polarity Check PH PHC EHC 5 EH 6 Sync Sep Clamp Pulse Generator Exist Check 8 23 HD SEL VD HD
2 VS IN 1 Polarity Check PV
10 9
CLAMP TIMING
VIDEO IN
7
Bias 19 18 17 16 15 21 22 14 11 24
IN/EXT
V IN
PV
EH
EV
V OUT
V REF
GND
PH
(SDIP)
PVC EVC
2 VS IN 1 Polarity Check PV
3 V. Ramp Generator Exist Check EV 18 Logic HD
CS IN
4
Polarity Check PH
Exist Check
VCC
8
HD SEL
21 VD EH
PHC EHC
5 6 Sync Sep Clamp Pulse Generator
10 9
CLAMP TIMING
VIDEO IN
7
Bias 17 16 15 14 13 19 20 12 11 22
IN/EXT
V IN
PV
EH
EV
V OUT
V REF
GND
PH
-2-
VCC
CXA1616N/S
Pin Description Pin No. SDIP SSOP
VCC 200k
(Ta = 25C, VCC = 12V) Pin voltage Equivalent circuit Description Inputs the vertical separate sync. Inputs at TTL level and polarity is positive/negative. V Low 0.5V V High 4.5V Connect a pull-down resistance of 470k or less to GND.
Symbol
1
1
VS IN
--
1
1k 20k
8k
8k
VCC
2
2
48k
PVC 0.3, 3.4V
96k 2 1k 8k 32k 32k
5
5
PHC
Connection pin of an integral capacitor for the polarity discriminator circuit (Polarity Check); connects a 0.22F capacitor to GND. When the capacitor is connected at positive polarity: 3.4V; negative polarity: 0.3V. No input : 3.7V. Vertical ramp waveform generator. Generates a ramp waveform synchronized to the input separate sync frequency. Connects a 0.68F capacitor to GND. The charging time constant (rising edge) of ramp waveform is determined by the 2k resistance and the external 0.68F capacitor, and the discharging time constant (falling edge) by the external 0.68F capacitor and the internal 17A current. When there is a verticai separate sync, the voltage at Pin 3 rises between 5.5 and 7.9V, existence discrimination (Exist Check) is performed, and an input signal is judged to exist. The voltage is 4.3V when no input signal exists.
VCC 5V 48k 2k
3
3
EVC
4.3 to 7.9V
3 8k 32k 17A
VCC 72k 2k 100A
4
4
CS IN
4.2V
200 4 400k 4V
Inputs the composite and horizontal separate sync (positive/negative polarity). Amplitude is 1 to 5Vp-p. Input through a capacitor.
-3-
CXA1616N/S
Pin No. SDIP SSOP
Symbol
Pin voltage
Equivalent circuit
Description Connects a quasi-peak hold circuit with a 33k resistance and 0.22F capacitor to discriminate input signal existence during composite sync input. When there is a composite sync, the voltage is held by the quasi-peak hold circuit at 4.2 to 4.8V. This voltage is then compared to a 3.8V reference voltage, and an input signal is judged to exist. The voltage is 3.0V when no input signal exists. Inputs the sync-on video (sync is negative polarity). Connect a 0.47F capacitor and a 270 resistance in series between the pin and its signal source. The slice level is determined by the relationship between the sync frequency and Pulse width and the sum of the 200 internal resistance and the 270 external resistance multiplied by the 29A current. V 29A x (T2/T1) x (200 + 270)
VCC 200 6 20k 8k
6
6
EHC
3.0, 4.8V
1k 3.8V 30A 16k
1k 12k
VCC
8.3V 5.8V 4k
7
7
VIDEO IN
4.5V
7
200
29A
16k
72k
V T1 4.5V 200k 70k T2
8
8
HD SEL
--
1k 8
Selects whether or not to output the VD interval portion of HD (H Drive Pulse). Input is at TTL Ievel. V Low 0.5V V High 2.0V Low level: The VD interval HD is not output. High level or open: The VD interval HD is output as is.
VCC
100
10k
9
9
TIMING
10.5V
9 1k 30A 17k
Connect a desired capacitor and a 12k resistance in parallel to GND. This capacitor changes the output pulse width of clamp pulse. (See Fig. 1)
-4-
CXA1616N/S
Pin No. SDIP SSOP
Symbol
Pin voltage
VCC
Equivalent circuit
Description
56k 2.7V
10
10
CLAMP
0.15V
10
10k
Clamp pulse output. This is an open collector at positive polarity.
5k
11
11
GND
0V
VCC 1k
--
GND Reference for the vertical sync separator circuit. Connect an external resistance between Vcc and GND to apply the reference voltage. Based on 4.4V. (See Fig. 2)
12 1k ( 14 )
12
14
V REF
--
20 ( 22 ) 30A 16k
36k
4.5V
13 14 15 16 17
15 16 17 18 19
IN/EXT EH EV PH PV
20k 13 14
0.12, 4.5V
15 16 17 8k 15 16 17 18 19
Outputs the polarity and existence information of a sync signal. See "Description of Operation" for their l/O matrix.
VCC
8k
8k
18
20
HD
0.15V
18 ( 20 )
8k 10k
HD (H Drive Pulse) output. This is an open collector at positive polarity.
VCC 45k 19 ( 21 ) 2k 60k 15k
19
21
V OUT
2.3V
Outputs the sync signal separated from the composite sync or sync-on video for the vertical sync separator. Positive polarity output at an amplitude of 2.3 to 6.0V.
-5-
CXA1616N/S
Pin No. SDIP SSOP
Symbol
Pin voltage
Equivalent circuit
Description Input for vertical sync separation comparator. Connect an integrator with a 3.9k resistance and a 3300pF capacitor between Pins 19 and 20. The comparator operates when the voltage of the integrated sync signal at the vertical interval becomes higher than the voltage which lowers by VBE (approximately 0.7V) from the voltage at Pin 12.
VCC 1k 12 1k ( 14 )
20
22
V IN
--
20 ( 22 ) 30A 16k
36k
VCC
8k
8k
21
23
VD
0.15V
21 ( 23 )
8k 10k
VD (V Drive Pulse) output. This is an open collector at positive polarity.
22
24
VCC
12V
--
Power supply.
-6-
CXA1616N/S
Electrical Characteristics No. Item
Symbol
(Ta = 25C, VCC = 12V, See the Electrical Characteristics Test Circuit) Measurement description Measures the height of the VD output wave for VS (vertical sparate sync) input. Input signal A (tw = 12.5s). 5V output power supply, RL = 2.2k. Measures the width of the VD output pulse for VS (vertical separate sync) input. Input signal A (tw = 12.5s). Measures the width of the VD output pulse for CS (composite sync) input. Input signal B (tw = 12.5s) Measures the width of the VD output pulse for VIDEO IN (sync-on video) input. Input signal C (tw = 12.5s). Measures the height of the HD output wave for CS (composite sync) input. Input signal D (tw = 0.65s). 5V output power supply, R4 = 2.2k. Measures the width of the HD output pulse for CS (composite sync) input. , Input signal B (tw = 0.65s). Measures the width of the HD output pulse for VIDIEO IN (sync-on video) input. Input signal C (tw = 0.65s). Measures the hight of the clamp pulse output wave for CS (composite sync) input. Input signal B (tw = 0.65s). 5V output power supply, R15 = 2.2k. Measures the width of the clamp pulse output pulse for CS (composite sync) input. Input signal B. Connects Pin 9 to GND through a 560pF capacitor and a 12k resistance in parallel. Measures the width of the clamp pulse output pulse for VIDEO IN (sync-on video) input. Input signal C. Connects Pin 9 to GND through a 10nF capacitor and a 12k resistance in parallel. Measurement point VD Pin 21 Pin 23 Min. (H level) 4.85 (L level) 0 Typ. Max. Unit
1
VD output voltage
EVD
( ( ( ( ( ( (
( ( ( ( ( ( (
5.0 0.15
5.0 0.4
V V
2
VD output pulse width 1
tV1
VD Pin 21 Pin 23 VD Pin 21 Pin 23 VD Pin 21 Pin 23
11.5
12.5
13.5
s
3
VD output pulse width 2
tV2
6.5
10
12.5
s
4
VD output pulse width 3
tV3
6.5
10
12.5
s
5
HD output voltage
EHD
HD Pin 18 Pin 20 HD Pin 18 Pin 20 HD Pin 18 Pin 20
(H level) 4.85 (L level) 0
5.0 0.15
5.0 0.4
V V
6
HD output pulse width 1
th1
0.5
0.65
0.8
s
7
HD output pulse width 2
th2
0.5
0.65
0.8
s
8
Clamp pulse ECP output voltage
CLAMP (Pin 10)
(H level) 4.85 (L level) 0
5.0 0.15
5.0 0.4
V V
9
Clamp pulse output pulse width 1
tC1
CLAMP (Pin 10)
--
0.25
--
s
10
Clamp pulse output pulse width 2
tC2
CLAMP (Pin 10)
3.7
4.1
4.5
s
-7-
CXA1616N/S
(Ta = 25C, VCC = 12V, See the Electrical Characteristics Test Circuit) No. Item
Symbol
Measurement description The voltage integral of the vertical polarity discrimination circuit for VS (vertical separate sync) input. Input signal F (negative logic). The voltage integral of the vertical polarity discrimination circuit for VS (vertical separate sync) input. Input signal G (positive Iogic).
Measurement point PVC (Pin 2)
Min.
Typ.
Max. Unit
11
PVC voltage 1 VPV1
--
0.3
--
V
12
PVC voltage 2 VPV2
PVC (Pin 2)
--
3.4
--
V
13
The voltage integral of the vertical polarity discrimination circuit for PHC voltage 1 VPH1 CS (composite sync) input. Input signal H (negative logic). The voltage integral of the vertical polarity discrimination circuit for PHC voltage 2 VPH2 CS (composite sync) input. Input signal I (positive logic). Measures the voltage of the vertical ramp waveform generator for VS (vertical separate sync) input. Input signal A. Measures the voltage of the vertical ramp waveform generator for VS (vertical separate sync) input. No input signal.
PHC (Pin 5)
--
0.4
--
V
14
PHC (Pin 5)
--
3.4
--
V
15
EVC voltage 1 VEV1
EVC (Pin 3)
--
7.9
--
V
16
EVC voltage 2 VEV2
EVC (Pin 3)
--
4.3
--
V
17
Measurers the sync existence discrimination voltage for EHC voltage 1 VEH1 CS (composite sync) input. Input signal J. Measures the sync existence discrimination voltage for EHC voltage 2 VEH2 CS (composite sync) input. No input signal. Measures the delay difference between CS and HD for CS (composite sync) Input. The time from the CS (negative polarity) fall time (50%) to the HD output rise time (50%). Input signal B. Measures the delay difference between CS and HD for CS (composite sync) input. The time from the CS (positive polarity) rise time (50%) to the HD output rise time (50%). Input signal D.
EHC (Pin 6)
--
4.8
--
V
18
EHC (Pin 6)
--
3.0
--
V
19
HD delay 1
td1
(
HD Pin 18 Pin 20
(
120
190
250
ns
20
HD delay 2
td2
(
HD Pin 18 Pin 20
(
120
205
260
ns
-8-
CXA1616N/S
(Ta = 25C, VCC = 12V, See the Electrical Characteristics Test Circuit) No. Item
Symbol
Measurement description Measures the delay difference between the input signal sync and HD for VIDEO IN (sync-on video) input. The time from the input sync fall time (50%) to the HD output rise time (50%). Input signal C. Compares the delay differences from both the VIDEO IN (sync-on video) input and the CS (composite sync) input to the HD output. (Compares Measurement No. 19 to 21). Measures the delay difference between HD and the clamp pulse for CS (composite sync) input. The time from the HD output fall time (50%) to the clamp pulse output rise time (50%). Input signal B. Measures the delay difference between HD and the clamp pulse for CS (composite sync) input. The time from the HD output fall time (50%) to the clamp pulse output rise time (50%). Input signal D. Measures the delay difference between HD and the clamp pulse for VIDEO IN (sync-on video) input. The time from the HD output fall time (50%) to the clamp pulse output rise time (50%). Input signal C. Polarity and existence information output of the sync signal. Measures the High level voltage under no load condition. Polarity and existence information output of the sync signal. Measures the Low level voltage under no load condition. Vcc = 12V, measures the current consumption for no input signal.
Measurement point HD Pin 18 Pin 20
Min.
Typ.
Max. Unit
21
HD delay 3
td3
(
(
110
180
240
ns
22
HD delay difference
thd
(
HD Pin 18 Pin 20
(
--
25
40
ns
23
Clamp pulse delay 1
tcd1
CLAMP (Pin 10)
110
140
180
ns
24
Clamp pulse delay 2
tcd2
CLAMP (Pin 10)
110
140
180
ns
25
Clamp pulse delay 3
tcd3
CLAMP (Pin 10)
90
130
170
ns
26
Logic output voltage High
QH
( (
Q1 to Q4 Pin13 to17 Pin15 to19 Q1 to Q4 Pin13 to17 Pin15 to19 VCC Pin 22 Pin 24
( (
3.5
4.5
5.0
V
27
Logic output voltage Low
QL
0
0.12
0.4
V
28
Current consumption
ICC
(
(
18
27
35
mA
-9-
CXA1616N/S
Signal Source Types Signal Item V. SYNC IN (Pin 1) fV = 40Hz tWV = 12.5s Negative logic 1Vp-p
V
Composite SYNC IN (Pin 4)
VIDEO IN (Pin 7)
A
1, 2, 15 tWV
fV = 40Hz
tWV = 12.5s
tWV Negative logic 1Vp-p fH = 130kHz tWH = 0.65s Negative logic 1Vp-p
V 0.7V 10H 12.5s 3H 0.2V
B
3, 6, 8, 9, 19, 23
H
tWH
C
4, 7, 10, 21, 25
H 5.8s
fV = 40Hz tWV = 12.5s
0.7V 1.5s 0.65s 0.2V
fH = 130kHz
tWH = 0.65s
fH = 130kHz D 5, 20, 24 fV = 200Hz tWV = 0.3ms Negative logic 5Vp-p fV = 200Hz tWV = 0.3ms Positive logic 5Vp-p fH = 130kHz tWV = 0.65s Negative logic 5Vp-p fH = 130kHz tWV = 0.65s Positive logic 5Vp-p fH = 15kHz tWV = 3.3s Negative logic 1Vp-p - 10 -
tWH = 0.65s
Positive logic 1Vp-p
F
11
G
12
H
13
I
14
J
17
CXA1616N/S
Electrical Characteristics Test Circuit (SSOP)
VIDEO IN 75
CS IN 75
VS IN 75 C1 C2 470p 220 1 VS IN PVC 2 PVC C3 EVC 0.22 3 EVC V IN 22 R2 3.9k 4 CS IN V OUT 21 VD 23 VD C5 3300p IN VCC 24 R1 2.2k VCC 12V
75 R18 75
R3 75
75
C4 0.22 C6 4.7 5 PHC EHC 6 EHC R6 C9 270 0.47 7 VIDEO IN 1SS119 8 HD SEL TIMING R13 12k 9 TIMING CLAMP 10 CLAMP R15 2.2k 11 GND V REF 14 IN/EXT 15 EV 17 PH 18 PV 19 HD 20
OUT HD R4 2.2k PV
C7 0.1 R5 33k C8 0.22 R10 4.7k R11 10k C10 3.3 S1 C11 560p
R7 75
75
PH
EV
EH 16
EH
IN/EXT R16 68k REF R17 39k
12 NC
NC 13
5V Output power supply
- 11 -
CXA1616N/S
Electrical Characteristics Test Circuit (SDIP)
VIDEO IN 75
CS IN 75
VS IN 75 C1 C2 470p 220 1 VS IN PVC 2 PVC C3 EVC 0.22 3 EVC V IN 20 R2 3.9k 4 CS IN V OUT 19 VD 21 VD C5 3300p IN VCC 22 R1 2.2k VCC 12V
75 R18 75
R3 75
75
C4 0.22 C6 4.7 5 PHC EHC 6 EHC R6 C9 270 0.47 7 VIDEO IN 1SS119 8 HD SEL TIMING R13 12k 9 TIMING CLAMP 10 CLAMP R15 2.2k 11 GND V REF 12 IN/EXT 13 EV 15 PH 16 PV 17 HD 18
OUT HD R4 2.2k PV
C7 0.1 R5 33k C8 0.22 R10 4.7k R11 10k C10 3.3 S1 C11 560p
R7 75
75
PH
EV
EH 14
EH
IN/EXT R16 68k REF R17 39k
5V Output power supply
- 12 -
CXA1616N/S
Description of Operation Input Signals * VS IN (Pin 1) fv: 40 to 200Hz Vs: 1 to 5Vp-p (positive/negative polarity) 1.5 to 5Vp-p (positive/negative polarity, for capacitor input) * CS IN (Pin 4) fH: 15k to 130kHz Vs: 1 to 5Vp-p (positive/negative polarity) * Video IN (Pin 7) fH: 15k to 130kHz fv: 40 to 200Hz V: 0 to 2.1Vp-p Vs: 0.2 to 0.6Vp-p
Waveform of VS IN, CS IN Vs and Cs
Waveform of Video IN V Vs
Clamp Pulse Output * The clamp pulse (Pin 10) is output under the conditions described in 1 and 2 below. When output with Pin 10 operating as an open collector, its polarity is positive. td: 130 to 140ns delay to HD output tw: Clamp pulse width is variable from 200ns to 3s depending on the capacitor value connected to Pin 9.
HD Clamp pulse td tw
1) Clamp pulse is not output during the VD interval for CS IN or Video IN.
Sync
Clamp pulse VD interval
2) Clamp pulse is output during the VD intenal for HS and VS separate sync. l/O Delay Time Difference
Video IN (Pin 7) sync waveform CS IN (Pin 4) separate sync waveform
HD (Pin 18) waveform td1
HD (Pin 18) waveform td2
td1: Delay time between Video IN (Pin 7) input and HD (Pin 18) output td2: Delay time between CS IN (Pin 4) input and HD (Pin 18) output td1, td2 = 200 to 260ns | td1 - td2 | = to 30ns to
- 13 -
CXA1616N/S
HD Selection Function HD SEL Low: The VD interval HD is not output. High: The VD interval HD is output as is.
HD VD interval HD VD interval
Mode Matrix of Sync Polarity Discrimination Signal CS IN (Pin 4) HD, COMP (positive polarity) HD, COMP (negative polarity) VS IN (Pin 1) No signal VD (positive) VD (negative) No signal VD (positive) VD (negative) No signal VD (positive) VD (negative) EH out (Pin 14) H H H H H H L L L EV out (Pin 15) L H H L H H L H H PH out (Pin 16) L L L H H H L L L PV out (Pin 17) L L H L L H L L H Sync IN/EXT (Pin 13) H H H H H H L H H
No signal
Low level: 0 to 0.2V, High level: 4.5 to 4.7V
I/O Matrix VS IN O -- -- -- CS IN O O -- -- VIDEO IN O -- VD OUT VS CS VIDEO (VIDEO) HD OUT CS CS VIDEO (VIDEO) O: signal input --: no signal : unrelated to input signal
- 14 -
Operation and Waveforms (SSOP)
fV = 40 to 200Hz Vs = 1.0 to 5.0Vp-p 1.5 to 5.0Vp-p (For capacitor input)
PVC
2 3 EV 20 Logic 4 8 23 EH EHC 6 CLAMP 10 9 Bias 19 18 17 16 15 21 22 14 11 24 560p to 10000p TIMING PHC 5 PH Polarity Check Exist Check HD SEL VD HD V. Ramp Generator Exist Check VS IN 1 PV CS IN Polarity Check
fH = 15k to 130kHz Vs = 1.0 to 5.0Vp-p
to 470k
VIDEO IN 7 Sync Sep
EVC
EV
PV
V IN
IN/EXT
V OUT
V REF
GND
VCC
VV = 0 to 2.1Vp-p Vs = 0.2 to 0.6Vp-p
PH
EH
- 15 -
Clamp Pulse Generator
tw = 200ns to 3s 12k
12V TYP
CXA1616N/S
Operation and Waveforms (SDIP)
fV = 40 to 200Hz Vs = 1.0 to 5.0Vp-p 1.5 to 5.0Vp-p (For capacitor input)
PVC
2 3 EV 18 Logic 4 8 21 EH EHC 6 CLAMP 10 9 Bias 17 16 15 14 13 19 20 12 11 22 560p to 10000p TIMING PHC 5 PH Polarity Check VD Exist Check HD SEL HD V. Ramp Generator Exist Check 1 PV Polarity Check
VS IN
fH = 15k to 130kHz Vs = 1.0 to 5.0Vp-p
to 470k
CS IN
VIDEO IN 7 Sync Sep
EVC
EV
PV
V IN
IN/EXT
V OUT
V REF
GND
VCC
VV = 0 to 2.1Vp-p Vs = 0.2 to 0.6Vp-p
PH
EH
- 16 -
Clamp Pulse Generator
tw = 200ns to 3s 12k
12V TYP
CXA1616N/S
CXA1616N/S
4.0 VCC = 12V Ta = 25C
3.0
Pulse width [s]
2.0
1.0 0 2000 4000 6000 8000 Pin 9 external capacitance [pF] 10000
Fig. 1. Clamp pulse output pulse width characteristics
13 For 12.5s input width from composite sync or sync-on video. VCC = 12V, Ta = 25C 12
Pulse width [s]
11
10
9
8
7
4.3
4.4 4.5 Pin12 reference voltagte [V] (Pin14)
4.6
Fig. 2. VD output pulse width characteristics
- 17 -
CXA1616N/S
Application Circuit (SSOP)
VIDEO IN 75 CS IN 75 VS IN 75 C1 C2 470p 220 1 VS IN VCC 24 R1 2.2k 2 PVC C3 0.22 3 R3 75 75 C4 0.22 4 CS IN C7 0.1 R5 33k C8 0.22 C6 4.7 5 PHC HD 20 R4 2.2k 6 EHC R6 C9 270 0.47 7 VIDEO IN HD SEL 8 HD SEL R13 12k 9 TIMING C11 560p CLAMP 10 CLAMP R15 2.2k 11 GND V REF 14 R17 39k 12 NC NC 13 IN/EXT 15 R16 68k IN/EXT EH 16 EH EV 17 PH 18 PH PV 19 PV V OUT 21 HD EVC V IN 22 R2 3.9k VD 23 VD C5 3300p VCC 12V
75 R18 75
R7 75
75
EV
5V
Note)Connect a resistance of 470k or less between Pin 1 and GND when inputting to VS IN (Pin 1) through a capacitor. Consider sags in determining the constant setting. Make input signal amplitude 1.5 to 5.0Vp-p for capacitor input.
C12 VS IN R18 to 470k 1 VS IN
Application circuit with VS IN (Pin 1) capacitor input
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 18 -
CXA1616N/S
Application Circuit (SDIP)
VIDEO IN 75 CS IN 75 VS IN 75 C1 C2 470p 220 1 VS IN PVC 2 PVC C3 EVC 0.22 3 R3 75 75 C4 0.22 4 CS IN C7 0.1 R5 33k C8 0.22 R10 4.7k R11 10k C10 3.3 S1 C11 560p C6 4.7 5 PHC EHC 6 EHC R6 C9 270 0.47 7 VIDEO IN 1SS119 8 HD SEL TIMING R13 12k 9 TIMING CLAMP 10 CLAMP R15 2.2k 11 GND V REF 12 R17 39k IN/EXT 13 R16 68k REF IN/EXT EV 15 EV PH 16 PH PV 17 HD 18 R4 2.2k PV V OUT 19 EVC V IN 20 R2 3.9k C5 3300p VD 21 VD IN VCC 22 R1 2.2k VCC 12V
75 R18 75
OUT HD
R7 75
75
EH 14
EH
5V Output power supply
Note)Connect a resistance of 470k or less between Pin 1 and GND when inputting to VS IN (Pin 1) through a capacitor. Consider sags in determining the constant setting. Make input signal amplitude 1.5 to 5.0Vp-p for capacitor input.
C12 VS IN R18 to 470k 1 VS IN
Application circuit with VS IN (Pin 1) capacitor input
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 19 -
CXA1616N/S
Package Outline CXA1616N
Unit: mm
24PIN SSOP(PLASTIC)
+ 0.2 1.25 - 0.1 7.8 0.1 0.1 13
24
A
1 + 0.1 0.22 - 0.05
12 + 0.05 0.15 - 0.02 0.65 0.1 0.1
0.13 M
5.6 0.1
0 to 10 NOTE: Dimensions "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-24P-L01 SSOP024-P-0056 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g
CXA1616S
+ 0.4 19.2 - 0.1
22PIN SDIP (PLASTIC)
+ 0.1 0.05 0.25 -
12
22
+ 0.3 6.4 - 0.1
0.5 0.2
1 1.778
11
0.5 0.1 + 0.15 0.9 - 0.1
+ 0.15 3.25 - 0.2
0.51 MIN
+ 0.4 3.9 - 0.1
7.62
0 to 15
Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type.
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-22P-01 SDIP022-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.95g
- 20 -
7.6 0.2

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